Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.

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For example, a single CD can be used to make a chain of 3 inverters, an inverter plus two transmission gates, or a complex logic gate. During the transparent phase of the latch, i. What to do in the lab report Attach screen shots for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete. The two inverters can be built from a CD by making the following connections: There are many advantages of CMOS, with the biggest being zero standby power consumption, at least ideally.

Observe the output on DIO8. Enter search terms or a module, class or function name. Show 3 screen shots of inverter outputs. Application of Cd datasheet logic. The two transmission gates work in tandem to cd datasheet the D-latch. Normally one would use anti-static mats and wrist straps when working with static sensitive electronics. Determine the logic function implemented by the following connections to a CD Find the Vds at which the drain current saturates, defined as Vdsat, for all Vgs measured from the Ids-Vds curves.

The CDBM CDBC stage static shift register is comprised of four separate shift register sections two sec- tions of four stages and two sections of five. Thus, the input to the first inverter is close to the voltage at node C. It is shown in the dashed box cd datasheet as chip 2 in Figure 7 above.

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Created using Sphinx 1. The other two pairs are more general purpose.

Estimate Vtn from Ids-Vgs curves. Draw an cd circuit for the following c4d007 description using a CD What to do in lab report Show 3 screen shots of inverter outputs.

Make a pin-level wiring diagram for a transmission gate using a CD You can download dagasheet view the data sheet cd datasheet or here. A steady high should appear. Attach screen shots for different Cd datasheet.

You should take a total of three screenshots, one each, corresponding to each inverter output. Connect pins 2,9 to CH0, and pins 4,11 to CH1.


Measure the Ids-Vds curves for a multiple Vgs values. Ids-Vgs in a saturation by connection configuration, e.

It should look as shown datashest Figure 7. Proceed as shown in Figure 6. Remove all the connections to the ALD chip shown in the dashed box cd datasheet Figure 3. It should look as shown in Figure 8. A circuit symbol description of the two pairs of transistors from the data sheet is shown below in figure 1.

You should see that DIO8 is also low. You do not have to draw a gate level schematic if you can determine the logic function implemented. When specifying wiring between the pins dataaheet an IC, engineers often use a shorthand for connections. Remember that chips 2 and 4 shown in Figure 8 need Vdd and Ground connections. What to do in the lab report Submit all screen shots. Describe the differences between the screenshots other than that they are inverted.

Can you tell what it does? This is the transparent phase of the latch. Have your GTA sign cd datasheet on each part before proceeding to the datadheet part. In which region should it be operating when it datashete an open switch? The CD includes diodes to protect it from static discharge, but it can still be damaged if it is not handled carefully. CMOS inverter schematic for voltage transfer measurement.

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Thank cd datasheet for keeping our lab clean and organized. Clean up Previous datashset 7. This is because CMOS logic requires a voltage input of 0-Vdd and the function generator always provides a waveform with a dc component of 0 V.

Connect pin 4, which serves as Q output of the latch to DIO8. How does changing R1 and C1 affect the frequency of the output? Measure the output voltage of the second inverter and the voltage across the capacitor with the scope. Set the function generator to output a Hz sine wave, 5vpp, 2. Estimate Vtn from Ids-Vgs curves. Try increasing the frequency and see at what frequency the inverter has trouble completing high to low and low to high transitions.